Renesas RH850/F1Kx Series Hardware Design Guide

RH850/F1Kx, RH850/F1K Series Hardware Design Guide
R01AN3841ED0110 Rev. 1.10 Page 77 of 108
August 8, 2019
Pin
Recommended Connection of Unused Pin
JP0 (excluding JP0_4) – General-purpose I/O
Mode
Input state
- Leave open (PIBCn_m = 0 and PMCn_m = 0)
- Connect to EVCC or EVSS via resistor (PIBCn_m
= 1 and PMCn_m = 1)
Output state
- Leave open
JP0_4 – General-purpose I/O Mode
Connect to EVSS via a resistor
Note2
JP0 – Debug Mode
(LPD IF / Nexus IF)
Note1
DCUTDI/LPDI/LPDIO (JP0_0): Connect to EVCC
via a resistor
DCUTDO/LPDO (JP0_1): Leave open
DCUTCK/LPDCLK (JP0_2): Leave open
DCUTMS (JP0_3): Connect to EVCC via a resistor
DCUTRST
(JP0_4): Connect to EVSS via a
resistor
Note2
DCURDY
/LPDCLKOUT (JP0_5): Leave open
Notes
1.
This part describes the handling of JP0 debug port pins during operation mode when the debug
interface is not in operation. For details of the different interfaces, see Chapter 8, Development Tool
Interface.
2.
When the Nexus interface is used for debugging the value of the resistor depends on the 3
rd
party
development tool specification.
Caution
When the debug mode is configured by OPBT0 on the RH850/F1KM-S1, the corresponding pins of the JP0 port
group are automatically switched to the selected debug interface. The remaining pins of JP0 can be used as
general-purpose I/O pin including its alternate function. Port usage details are described in the debug interface
connection chapter.

Renesas RH850/F1Kx Series Specifications

General

Brand	Renesas
Model	RH850/F1Kx Series
Category	Computer Hardware
Language	English