SBC PCD2.M5 Series - Default Chapter; Table of Contents

Hardware Manual for the PCD2.M5 Series│Document 26/856; Version EN 12│2014-07-24
Saia-Burgess Controls AG
PCD2.M5_
Contents
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0.1 Document-History ........................................................................................... 0-6
0.2 Trademarks ..................................................................................................... 0-6
1 Graphical index
2 Overview
2.1 Introduction ..................................................................................................... 2-1
2.2 Instructions for connecting Saia-PCD
®
controllers to the internet ................... 2-1
2.3 Planning an application with PCD2.M5_ components .................................... 2-2
2.4 Cabling ............................................................................................................ 2-3
2.4.1 Cable routing ................................................................................................... 2-3
2.5 Addressing ...................................................................................................... 2-4
2.6 HW Overview .................................................................................................. 2-5
2.6.1 PCD2.M5xx0 ................................................................................................... 2-5
2.6.2 PCD2.C2000 and PCD2.C1000 ...................................................................... 2-5
3 PCD2.M5xx0 CPUs and module holders
3.1 System overview ............................................................................................. 3-1
3.2 General technical details ................................................................................. 3-3
3.3 System resources ........................................................................................... 3-5
3.3.1 Program blocks ............................................................................................... 3-5
3.3.2 Computation ranges for count types ............................................................... 3-5
3.3.3 Media .............................................................................................................. 3-5
3.4 PCD2.M5_ CPUs ............................................................................................ 3-6
3.4.1 Block diagram for PCD2.M5_ ......................................................................... 3-8
3.4.2 HardwareandrmwareversionsforthePCD2.M5_ ...................................... 3-9
3.4.3 Extensions with various module holders ......................................................... 3-10
3.4.4 Expansion housings ........................................................................................ 3-11
3.4.5 Addressing of module holders and modules ................................................... 3-15
3.4.6 Decentralised expansion of RIO with PCD3 components ............................... 3-16
3.4.7 Dimensions ..................................................................................................... 3-17
3.5 Mounting ......................................................................................................... 3-18
3.5.1 Mounting position and ambient temperature ................................................... 3-18
3.5.2 Remove cover from housing ........................................................................... 3-19
3.5.3 Replace housing cover ................................................................................... 3-20
3.5.4 Remove upper part of housing ........................................................................ 3-21
3.5.5 Replace housing cover ................................................................................... 3-22
3.5.6 I/O module slots .............................................................................................. 3-22
3.6 Installation and addressing of PCD2 I/O modules .......................................... 3-23
3.6.1 Insertion of I/O modules .................................................................................. 3-23
3.6.2 Address and terminal designation ................................................................... 3-23
3.7 Power supply, earthing scheme, cable layout ................................................. 3-24
3.7.1 External power supply ..................................................................................... 3-24
3.7.2 Internal power supply ...................................................................................... 3-25
3.7.3 Earthing concept ............................................................................................. 3-25
3.7.4 Cable layout .................................................................................................... 3-26
3.8 Operating states .............................................................................................. 3-27
3.9 Connections to PCD2.M5_ ............................................................................. 3-28
3.10 Partitioning options for user memory .............................................................. 3-30
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