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Sun Microsystems UltraSPARC-I - S_Rto;S_Err; S_Req

Sun Microsystems UltraSPARC-I
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Sun Microelectronics
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7. UltraSPARC External Interfaces
7.8.4 NonCachedBlockWrite (P_NCBWR_REQ)
Noncached Block Write Request. UltraSPARC writes 64 bytes of noncached data.
Generated by UltraSPARC for block store to a noncached address space.
The data is aligned on 64-byte boundary (PA<5:4>=0).
SC issues S_WAB to the requesting UltraSPARC to drive the data on SYSDATA.
7.9 S_RTO/S_ERR
UltraSPARC changes the E-Cache tag to I state whenever a P_RD*_REQ for that
lines receives S_RTO or S_ERR reply.
When UltraSPARC issues a P_REQ for ownership of a line in S or O state, of the
reply is S_RTO or S_ERR, the state of the line is not changed (tag or data) and the
store is not completed.
7.10 S_REQ
UltraSPARC-I can support at most one outstanding S_REQ transaction for copy-
back/invalidate from SC. SC must block subsequent S_REQs to the same
UltraSPARC-I, even when the requests are from different UltraSPARCs and for
data at different addresses.
UltraSPARC-I also imposes the following restrictions on back-to-back S_REQs:
If the previous S_REQ requires a data transfer, the earliest that SC can send
the next S_REQ (both S_INV_REQ and S_CP*_REQ) is in the clock cycle
following the S_REPLY that transfers the data.
If the previous S_REQ does not require a data transfer (both S_INV_REQ and
P_SNACK reply to a preceding S_CP*_REQ), the earliest that SC can send the
next S_REQ (both S_INV_REQ and S_CP*_REQ) is in the clock cycle following
the P_REPLY for the previous S_REQ.
UltraSPARC is allowed to issue unrelated transactions before it provides the
P_REPLY to an outstanding S_REQ. In this case, however, SC is not required to
make SYSADDR available or to complete any of these unrelated transactions un-
til UltraSPARC issues its P_REPLY for the outstanding S_REQ.
If NDP=0, there are a minimum of 2 system cycles between an S_REQ packet and
a P_REPLY. If NDP=1, the minimum increases to 5 system cycles. The maximum
depends on what the processor is doing with the E-Cache, and it is model depen-
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