Sun Microelectronics
290
UltraSPARC User’s Manual
An annulled load use or floating-point use will be treated as a dependent instruc-
tion until the N
2
Stage of the branch. For example:
If the annulling branch is grouped with a delay slot containing a load use, the
group will pay the full load use penalty even if the load use is annulled. This is
because the branch is not resolved until the use stall is released.
WR{PR}, SAVE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE are
stalled in the G Stage until earlier annulling branches are resolved, even if they
are not in the delay slot. This means that they cannot be dispatched in the same
group or the first three groups following an annulling branch instruction. For ex-
ample:
LDD{A}, LDSTUB{A}, SWAP{A} and CAS{X}A are stalled in the G Stage if there is a
delayed control transfer instruction in the E Stage or C Stage. For example:
17.7 Load / Store Instructions
Load / store instructions can be dispatched only if they are in the first three in-
struction slots. One load/store instruction can be dispatched per group. Load /
store instructions other than single group are: LD{SB,SH,SW,UB,UH,UW,X}{A},
LD{D}F{A}, ST{B,H,W,X}{A}, STF{A}, STDF{A}, JMPL, MEMBAR, STBAR, PREFETCH{A}.
LDD{A}, STD{A}, LDSTUB{A}, SWAP{A} will not dispatch younger instructions for
one clock after they are dispatched. CAS{X}A will not dispatch younger instruc-
tions for two clocks after they are dispatched.
Loads are not stalled on a cache miss, instead they are enqueued in the load buff-
er until data can be returned. Load data is returned in the order that loads are is-
sued, so a cache miss forces subsequent load hits to be enqueued until the older
load miss data is available.
FADD f7,f7,f6 GECN
1
N
2
N
3
W
Bcc, a (not taken) GECN
1
N
2
N
3
W
FADD f6,f7,f8 G flushed
FADD f6,f7,f8 GECN
1
N
2
Bicc, a GECN
1
N
2
N
3
W
SAVE GECN
1
N
2
Bicc GECN
1
N
2
N
3
W
LDD GECN
1
N
2
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