Sun Microelectronics
353
G. Differences Between UltraSPARC Models
155 ✓ E$ field of UPA_CONFIG register
155 ✓ ELIM field of UPA_CONFIG register
155 ✓ WB subfield in PCON field of UPA_CONFIG register
155 ✓ SCIQ0 subfield in PCON field of UPA_CONFIG register
155 ✓ Allowable combinations of values for WB and SCIQ0 subfields in PCON field of
UPA_CONFIG register
172 ✓✓VER.impl values
173 ✓ Reset values for MCAP field of UPA_CONFIG register
173 ✓ Reset values for CLK_MODE field of UPA_CONFIG register
173 ✓ Reset values for E$ field of UPA_CONFIG register
173 ✓ Reset values for ELIM field of UPA_CONFIG register
173 ✓ Reset values for WB subfield in PCON field of UPA_CONFIG register
173 ✓ Reset values for SCIQ0 subfield in PCON field of UPA_CONFIG register
194 ✓ PREFETCH{A} unimplemented
241 ✓✓VER.impl values
248 ✓ PREFETCH{A} unimplemented
248 ✓ PREFETCH{A} fcn=0..4 implemented
274 ✓✓D-Cache Miss, E-Cache hit latency depends on SRAM mode
275 ✓✓Load buffer depth optimized for 1–1–1 mode
277 ✓✓E-Cache accessed every other cycle in 2–2 mode
278 ✓✓Read-toWrite bus turnaround penalty in 1–1–1 mode only
284 ✓ CTI at end of cache line not dispatched until delay slot fetched
315 ✓ VA encoding to access 8 and 16 Mb E-Cache data fields
316 ✓ VA encoding to access 8 and 16 Mb E-Cache tag/state/parity fields
340 ✓✓Number of bits in ECAT interface
340 ✓✓Number of bits in ECAD interface
340 ✓ SCLK_MODE pin is present only in UltraSPARC-I
340 ✓ LOOP_CAP pin present only in UltraSPARC-I
340 ✓ PHASE_DET_CLK pin present only in UltraSPARC-II
340 ✓ ECACHE_22_MODE pin present only in UltraSPARC-II
340 ✓ MCAP pins present only in UltraSPARC-II
341 ✓✓Number of bits in ECAD interface
341 ✓✓Number of bits in ECAT interface
342 ✓ LOOP_CAP pin present only in UltraSPARC-I
343 ✓ E_BUS_CLKA signal present only in UltraSPARC-II
343 ✓ E_BUS_CLKB signal present only in UltraSPARC-II
Table G-1 UltraSPARC Model-Specific Information
Page I II Description
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