Sun Microelectronics
iii
Contents
Preface ..................................................................................................................................... 9
Overview ...................................................................................................................... 9
A Brief History of SPARC .......................................................................................... 9
How to Use This Book................................................................................................ 10
Section I — Introducing UltraSPARC
1. UltraSPARC Basics................................................................................................................ 3
1.1 Overview ...................................................................................................................... 3
1.2 Design Philosophy ...................................................................................................... 3
1.3 Component Overview ................................................................................................ 5
1.4 UltraSPARC Subsystem.............................................................................................. 10
2. Processor Pipeline................................................................................................................. 11
2.1 Introductions................................................................................................................11
2.2 Pipeline Stages............................................................................................................. 12
3. Cache Organization .............................................................................................................. 17
3.1 Introduction.................................................................................................................. 17
4. Overview of the MMU......................................................................................................... 21
4.1 Introduction.................................................................................................................. 21
4.2 Virtual Address Translation ...................................................................................... 21
Section II — Going Deeper
5. Cache and Memory Interactions ........................................................................................ 27
5.1 Introduction.................................................................................................................. 27
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