Sun Microelectronics
5
1. UltraSPARC Basics
1.3 Component Overview
Figure 1-1 shows a block diagram of the UltraSPARC processor.
Figure 1-1 UltraSPARC Block Diagram
The block diagram illustrates the following components:
• Prefetch and Dispatch Unit (PDU), including logic for branch prediction
• 16Kb Instruction Cache (I-Cache)
• Memory Management Unit (MMU), containing a 64-entry Instruction
Translation Lookaside Buffer (iTLB) and a 64-entry Data Translation
Lookaside Buffer (dTLB)
Ext.
Cache
RAM
Prefetch and Dispatch Unit (PDU)
Integer Execution Unit (IEU)
Floating Point Unit (FPU)
Graphics Unit (GRU)
Instruction Cache and Buffer
Grouping Logic Integer Reg and Annex
FP
Reg
FP Multiply
FP Add
FP Divide
Load / Store Unit (LSU)
Data Load Store
External Cache Unit (ECU)
Memory Management Unit (MMU)
Memory Interface Unit (MIU)
System Interconnect
Cache Buffer Buffer
iTLB dTLB
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