Sun Microelectronics
4
1. UltraSPARC Basics
The number of instructions for a given task depends on the instruction set and on
compiler optimizations (dead code elimination, constant propagation, profiling
for code motion, and so on). Since it is based on the SPARC-V9 architecture,
UltraSPARC offers features that can help reduce the total instruction count:
• 64-bit integer processing
• Additional floating-point registers (beyond the number offered in SPARC-V8),
which can be used to eliminate floating-point loads and stores
• Enhanced trap model with alternate global registers
The average number of cycles per instruction (CPI) depends on the architecture
of the processor and on the ability of the compiler to take advantage of the hard-
ware features offered. The UltraSPARC execution units (ALUs, LD/ST, branch,
two floating-point, and two graphics) allow the CPI to be as low as 0.25 (four in-
structions per cycle). To support this high execution bandwidth, sophisticated
hardware is provided to supply:
1. Up to four instructions per cycle, even in the presence of conditional
branches
2. Data at a rate of 16 bytes-per-cycle from the external cache to the data
cache, or 8 bytes-per-cycle into the register files.
To reduce instruction dependency stalls, UltraSPARC has short latency opera-
tions and provides direct bypassing between units or within the same unit. The
impact of cache misses, usually a large contributor to the CPI, is reduced signifi-
cantly through the use of de-coupled units (prefetch unit, load buffer, and store
buffer), which operate asynchronously with the rest of the pipeline.
Other features such as a fully pipelined interface to the external cache (E-Cache)
and support for speculative loads, coupled with sophisticated compiler tech-
niques such as software pipelining and cross-block scheduling also reduce the
CPI significantly.
A balanced architecture must be able to provide a low CPI without affecting the
cycle time. Several of UltraSPARC’s architectural features, coupled with an ag-
gressive implementation and state-of-the-art technology, have made it possible to
achieve a short cycle time (see Table 1-1). The pipeline is organized so that large
scalarity (four), short latencies, and multiple bypasses do not affect the cycle time
significantly.
Table 1-1 Implementation Technologies and Cycle Times
UltraSPARC-I UltraSPARC-II
Technology 0.5 µ CMOS 0.35 µ CMOS
Cycle Time 7 ns and faster 4 ns and faster
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...
Need help?
General