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UltraSPARC User’s Manual
dent; Table 7-15 shows the approximate values for different UltraSPARC models.
The worst case delay occurs when E-Cache fill(s), Writeback(s), and block store(s)
must first compete.
An S_REQ operates on the E-Cache atomically with respect to other cache events.
Invalidates do not necessarily propagate to the D-Cache until software completes
a store and a MEMBAR #StoreLoad. UltraSPARC’s internal behavior should not
matter to the system designer, as long as the application uses the appropriate
SPARC memory model. See The SPARC Architecture Manual, Version 9 for informa-
tion about memory models.
In systems without Dtags, SC sets NDP=1 in all S_REQs. In this case, UltraSPARC
must search its tag store to determine if the requested line is present. If not,
UltraSPARC replies with P_SNACK.
In systems with Dtags, SC sets NDP=0 in all S_REQs. This allows UltraSPARC to
reply (P_SACK{D}) without searching its tag store, which is a significant optimi-
zation.
All other effects are the same with both values of NDP.
7.11 Writeback Issues
UltraSPARC sets the Dirty Victim Pending (DVP) bit in a coherent read transac-
tion packet if the associated E-Cache miss victimized a dirty line. SC uses the
DVP bit to manage the Dtag state for the missed block.
Each Writeback transaction is always paired one-to-one with a read transaction
with the DVP bit set. Pairing means that UltraSPARC always generates both a
read and a Writeback for the same cache index. UltraSPARC always issues the
read transaction before the Writeback transaction, but the transactions can com-
plete in any order.
Table 7-15 Worst-Case Delay Between S_REQ and P_REPLY when NDP=1
UltraSPARC Model Cycles
UltraSPARC-I ~30
UltraSPARC-II ~50–60
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