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14. Implementation Dependencies
14.4.7 LDD/STD Handling (Impdep #107, 108)
LDD and STD instructions are directly executed in hardware.
Note: LDD/STD are deprecated in SPARC-V9. In UltraSPARC it is more
efficient to use LDX/STX for accessing 64-bit data. LDD/STD take longer to
execute than two 32-/64-bit loads/stores.
14.4.8 FP mem_address_not_aligned (Impdep #109, 110, 111, 112)
LDDF{A}/STDF{A} cause an
LDDF/STDF_ mem_address_not_aligned
trap if the ef-
fective address is 32-bit aligned but not 64-bit (doubleword) aligned.
LDQF{A}/STQF{A} are not directly executed in hardware; they cause an
illegal_instruction
trap.
14.4.9 Supported Memory Models (Impdep #113, 121)
UltraSPARC supports all three memory models (TSO, PSO, RMO). See Section
15.2, “Supported Memory Models,” on page 256.
14.4.10 I/O Operations (Impdep #118, 123)
I/O spaces and their accesses are specified in Section 5.3.7, “I/O and Accesses
with Side-effects,” on page 38.
14.5 Non-SPARC-V9 Extensions
14.5.1 Per-Processor TICK Compare Field of TICK Register
The SPARC-V9 TICK register is used for fine-grain measurements of time in pro-
cessor cycles. The TICK Compare field (TICK_CMPR) of the TICK Register pro-
vides added functionality for thread scheduling on a per-processor basis. Non
privileged accesses to this register will cause a
privileged_opcode
trap. See
Table 10-1, “Machine State After Reset and in RED_state,” on page 172 for a list of
resets states.
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