Sun Microsystems UltraSPARC-I - SYSADDR Bus Arbitration Protocol

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UltraSPARC User’s Manual

7.4 SYSADDR Bus Arbitration Protocol

This section speciﬁes the distributed arbitration protocol for driving a request

packet on the SYSADDR bus.

7.4.1 SYSADDR Bus Interconnection Topology

SYSADDR accommodates a maximum of four bus masters (which can be either

UltraSPARCs or I/O ports), as well as a System Controller (SC).

A master UltraSPARC cannot send a request directly to a slave. All transactions

are received by the SC and either serviced directly or forwarded to the proper re-

cipient. The SC delivers a transaction to a speciﬁc interconnect slave interface by

asserting that slave’s unique Addr_Valid signal. Note that in this discussion,

Memory is considered a slave.

A distributed arbitration protocol determines the current driver for the

SYSADDR bus and Addr_Valid. Although each Addr_Valid has only two poten-

tial drivers, the same enable logic can and should be used for both. Holding am-

pliﬁers in the System Controller must maintain the last state of Addr_Valid

whenever UltraSPARC or the SC stop driving it.

Figure 7-10 illustrates the interconnection topology for the SYSADDR bus. With

this topology, the arbiter logic can be implemented efﬁciently, without any inter-

nal muxing or demuxing of the input or output request signals.

Figure 7-10 SYSADDR Bus Interconnection Topology

SC_RQ

Req<3>

Req<2>

Req<1>

Req<0>

SYSADDR<35:0>

System Controller

Addr_Valid<3>

Addr_Valid<2>

Addr_Valid<1>

Addr_Valid<0>

port_ID<4:0> port_ID<4:0> port_ID<4:0> port_ID<4:0>

1:0=0 1:0=1 1:0=2 1:0=3

Node_RQ<2>

Node_RQ<1>

Node_RQ<0>

Node_RQ<2>

Node_RQ<1>

Node_RQ<0>

Nodex_RQ

RESET_L

UltraSPARC