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14. Implementation Dependencies
Note: UltraSPARC does not contain an FQ. An attempt to read the FQ with a
RDPR instruction causes an
illegal_instruction
trap.
Note: SPARC-V8-compatible programs should set the least significant bit of the
floating-point register number to zero for all double-precision instructions.
Violation of this SPARC-V8 architectural constraint may result in unexpected
program behavior.
qne: This bit is not used, because UltraSPARC implements precise floating-
point exceptions.
aexc: 5-bit accrued exception field accumulates IEEE 754 exceptions while
floating-point exception traps are disabled (that is, FSR.TEM=0).
cexc: 5-bit current exception field indicates the most recently generated IEEE
754 exceptions.
14.4 SPARC-V9 Memory-Related Operations
14.4.1 Load/Store Alternate Address Space (Impdep #5, 29, 30)
Supported ASI accesses are listed in Section 8.3, “Alternate Address Spaces,” on
page 146.
14.4.2 Load/Store ASR (Impdep #6,7,8,9, 47, 48)
Supported ASRs are listed in Section 8.4, “Ancillary State Registers,” on page 156.
14.4.3 MMU Implementation (Impdep #41)
UltraSPARC memory management is based on software-managed instruction and
data Translation Lookaside Buffers (TLBs) and in-memory Translation Storage
Buffers (TSBs) backed by a Software Translation Table. See Chapter 4, “Overview
of the MMU,” on page 21 for more details.
14.4.4 FLUSH and Self-Modifying Code (Impdep #122)
FLUSH is needed to synchronize code and data spaces after code space is modi-
fied during program execution. FLUSH is described in Section 5.3.2, “Memory
Synchronization: MEMBAR and FLUSH,” on page 32. On UltraSPARC, the
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