Sun Microelectronics
50
UltraSPARC User’s Manual
6.5 MMU Operation Summary
Table 6-4 on page 51 summarizes the behavior of the D-MMU; Table 6-5 on page
51 summarizes the behavior of the I-MMU for normal (non-UltraSPARC-internal)
ASIs. In each case, for all conditions the behavior of the MMU is given by one of
the following abbreviations:
The ASI is indicated by one the following abbreviations:
Note: The “*_LITTLE” versions of the ASIs behave the same as the big-endian
versions with regard to the MMU table of operations.
Other abbreviations include “W” for the writable bit, “E” for the side-effect bit,
and “P” for the privileged bit.
The tables do not cover the following cases:
• Invalid ASIs, ASIs that have no meaning for the opcodes listed, or non-
existent ASIs; for example, ASI_PRIMARY_NO_FAULT for a store or atomic.
Also, access to UltraSPARC internal registers other than LDXA, LDFA, STDFA
or STXA, except for I-Cache diagnostic accesses other than LDDA, STDFA or
STXA. See Section 8.3.2, “UltraSPARC (Non-SPARC-V9) ASI Extensions,” on
page 147. The MMU signals a
data_access_exception
trap (FT=08
16
) for this
case.
Abbrev Meaning
OK Normal Translation
DMISS
data_access_MMU_miss
trap
DEXC
data_access_exception
trap
DPROT
data_access_protection
trap
IMISS
instruction_access_MMU_miss
trap
IEXC
instruction_access_exception
trap
Abbrev Meaning
NUC ASI_NUCLEUS*
PRIM Any ASI with PRIMARY translation, except *NO_FAULT”
SEC Any ASI with SECONDARY translation, except *NO_FAULT”
PRIM_NF ASI_PRIMARY_NO_FAULT*
SEC_NF ASI_SECONDARY_NO_FAULT*
U_PRIM ASI_AS_IF_USER_PRIMARY*
U_SEC ASI_AS_IF_USER_SECONDARY*
BYPASS ASI_PHYS_* and also other ASIs that require the MMU to perform a bypass operation
(such as D-Cache access)
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