Sun Microelectronics
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6. MMU Internal Architecture
• An invalid LDA/STA ASI value, invalid virtual address, read to write-only
register, or write to read-only register, but not for an attempted user access to
a restricted ASI (see the
privileged_action
trap described below).
• An access (including FLUSH) with an ASI other than
ASI_{PRIMARY,SECONDARY}_NO_FAULT{_LITTLE} to a page marked with
the NFO (no-fault-only) bit.
• Virtual address out of range (including FLUSH) and PSTATE.AM is not set.
See Section 4.2, “Virtual Address Translation,” on page 21.
The
data_access_exception
trap also occurs when the D-MMU is disabled and one
the following occurs:
• Speculative (non-faulting) load or FLUSH instruction issued when
LSU_Control_Register.DP=0.
• An atomic instruction (including 128-bit atomic load) is issued using the
ASI_PHYS_BYPASS_EC_WITH_EBIT{_LITTLE} ASIs. In this case
SFSR.FT=04
16
.
6.4.5 Data_access_protection Trap
This trap occurs when the MMU detects a protection violation for a data access.
A protection violation is defined to be an attempted store to a page that does not
have write permission.
6.4.6 Privileged_action Trap
This trap occurs when an access is attempted using a restricted ASI while in non-
privileged mode (PSTATE.PRIV=0).
6.4.7 Watchpoint Trap
This trap occurs when watchpoints are enabled and the D-MMU detects a load or
store to the virtual or physical address specified by the VA Data Watchpoint Register
or the PA Data Watchpoint Register, respectively. See Section A.5, “Watchpoint Sup-
port,” on page 304.
6.4.8 Mem_address_not_aligned Trap
This trap occurs when a load, store, atomic, or JMPL/RETURN instruction with a
misaligned address is executed. The LSU signals this trap, but the D-MMU
records the fault information in the SFSR and SFAR.
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