Sun Microelectronics
48
UltraSPARC User’s Manual
Note: The
fast_instruction_access_MMU_miss
,
fast_data_access_MMU_miss
, and
fast_data_access_protection
traps are generated instead of
instruction_access_MMU_miss
,
data_access_MMU_miss
, and
data_access_protection
traps, respectively.
6.4.1 Instruction_access_MMU_miss Trap
This trap occurs when the I-MMU is unable to find a translation for an instruc-
tion access; that is, when the appropriate TTE is not in the iTLB.
6.4.2 Instruction_access_exception Trap
This trap occurs when the I-MMU is enabled and one of the following happens:
• The I-MMU detects a privilege violation for an instruction fetch; that is, an
attempted access to a privileged page when PSTATE.PRIV=0.
• Virtual address out of range and PSTATE.AM is not set. See Section 14.1.6,
“44-bit Virtual Address Space,” on page 237. Note that the case of JMPL/
RETURN and branch-CALL-sequential are handled differently. The contents
of the I-Tag Access Register are undefined in this case, but are not needed by
software.
6.4.3 Data_access_MMU_miss Trap
This trap occurs when the MMU is unable to find a translation for a data access;
that is, when the appropriate TTE is not in the data TLB for a memory operation.
6.4.4 Data_access_exception Trap
This trap occurs when the D-MMU is enabled and one of the following happens:
(the D-MMU does not prioritize these)
• The D-MMU detects a privilege violation for a data or FLUSH instruction
access; that is, an attempted access to a privileged page when
PSTATE.PRIV=0.
• A speculative (non-faulting) load or FLUSH instruction issued to a page
marked with the side-effect (E-bit)=1.
• An atomic instruction (including 128-bit atomic load) issued to a memory
address marked uncacheable in a physical cache; that is, with CP=0.
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