Sun Microelectronics
225
13. UltraSPARC Extended Instructions
13.6 Memory Access Instructions
13.6.1 Partial Store Instructions
Format (3):
Description:
The partial store instructions are selected by using one of the partial store ASIs
with the STDA instruction.
Two 32-bit, four 16-bit or eight 8-bit values from the 64-bit rd register are condi-
tionally stored at the address specified by rs1 using the mask specified by rs2. The
value in rs2 has the same format as the result generated by the pixel compare in-
structions (see Section 13.5.7, “Pixel Compare Instructions,” on page 217). The
Opcode imm_asi ASI Value Operation
STDFA
ASI_PST8_P C0
16
Eight 8-bit conditional stores to primary address
space
STDFA
ASI_PST8_S C1
16
Eight 8-bit conditional stores to secondary address
space
STDFA
ASI_PST8_PL C8
16
Eight 8-bit conditional stores to primary address
space, little-endian
STDFA
ASI_PST8_SL C9
16
Eight 8-bit conditional stores to secondary address
space, little-endian
STDFA
ASI_PST16_P C2
16
Four 16-bit conditional stores to primary address
space
STDFA
ASI_PST16_S C3
16
Four 16-bit conditional stores to secondary address
space
STDFA
ASI_PST16_PL CA
16
Four 16-bit conditional stores to primary address
space, little-endian
STDFA
ASI_PST16_SL CB
16
Four 16-bit conditional stores to secondary address
space, little-endian
STDFA
ASI_PST32_P C4
16
Two 32-bit conditional stores to primary address
space
STDFA
ASI_PST32_S C5
16
Two 32-bit conditional stores to secondary address
space
STDFA
ASI_PST832_PL CC
16
Two 32-bit conditional stores to primary address
space, little-endian
STDFA
ASI_PST32_SL CD
16
Two 32-bit conditional stores to secondary address
space, little-endian
Suggested Assembly Language Syntax
stda
freg
rd
,[
reg
rs1
]
reg
rs2
,
imm_asi
11 11 0111 rs2rd rs1
31 141924 18 13 02530 29 4
imm_asi
5
i=0
12
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