Sun Microelectronics
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A. Debug and Diagnostics Support
watchpoint is disabled. If the watchpoint is enabled and a data reference
overlaps any of the watched bytes in the watchpoint mask, a physical
watchpoint trap is generated.
A.7 I-Cache Diagnostic Accesses
The instruction cache (I-Cache) utilizes the Dynamic Set Prediction
1
technique to
realize a set-associative cache with a direct-mapped physical RAM design. The
direct-mapped RAM core is logically divided into two sets. Rather than using the
tag to determine which set contains the requested instructions, a set prediction
from the last access to the I-Cache is used to access the instructions for the cur-
rent fetch.
Figure A-5 Simplified I-Cache Organization (Only 1 Set Shown)
Each set of the I-Cache is divided into four fields per entry:
• The instruction field contains eight 32-bit instructions.
• The tag field contains a 28-bit physical tag and a valid bit.
• The pre-decode field contains eight 4-bit information packets about the
instructions stored.
• The next field contains the LRU bit, next address, branch and set predictions.
There is one physical LRU bit per I-Cache line (i.e. sixteen instructions) but it
is logically replicated for each set. There are four 2-bit dynamic branch
prediction (BRPD) fields, one for each two adjacent instructions. Two sets of
set prediction and next address fields, one for each four instructions.
1. For a description of the Dynamic Set Prediction technique, see the “Rapid Instruction (Pre)fetching and
Dispatching Using Prior (Pre)fetching Predictive Annotations” memo.
instruction
pre-decode
BRPD
sp
8×32b
8×4b4×2b2×11b
Cache
tag
28b
valid
1b
LRU
1b
next
2×1b
Lines
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