Sun Microelectronics
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SPARC-V9 Memory Models 15
15.1 Overview
SPARC-V9 defines the semantics of memory operations for three memory mod-
els. From strongest to weakest, they are Total Store Order (TSO), Partial Store Or-
der (PSO), and Relaxed Memory Order (RMO). The differences in these models
lie in the freedom an implementation is allowed in order to obtain higher perfor-
mance during program execution. The purpose of the memory models is to spec-
ify any constraints placed on the ordering of memory operations in uniprocessor
and shared-memory multi-processor environments. UltraSPARC supports all
three memory models.
Although a program written for a weaker memory model potentially benefits
from higher execution rates, it may require explicit memory synchronization in-
structions to function correctly if data is shared. MEMBAR is a SPARC-V9 memo-
ry synchronization primitive that enables a programmer to explicitly control the
ordering in a sequence of memory operations. Processor consistency is guaran-
teed in all memory models.
The current memory model is indicated in the PSTATE.MM field. It is unaffected
by normal traps, but is set to TSO (PSTATE.MM=0) when the processor enters
RED_state.
A memory location is identified by an 8-bit Address Space Identifier (ASI) and a
64-bit (virtual) address. The 8-bit ASI may be obtained from a ASI register or in-
cluded in a memory access instruction. The ASI is used to distinguish among and
provide an attribute to different 64-bit address spaces. For example, the ASI is
used by the UltraSPARC MMU and memory access hardware to control virtual-
to-physical address translations, access to implementation-dependent control and
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