Sun Microelectronics
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Cache and Memory Interactions 5
5.1 Introduction
This chapter describes various interactions between the caches and memory, and
the management processes that an operating system must perform to maintain
data integrity in these cases. In particular, it discusses:
• When and how to invalidate one or more cache entries
• The differences between cacheable and non-cacheable accesses
• The ordering and synchronization of memory accesses
• Accesses to addresses that cause side effects (I/O accesses)
• Non-faulting loads
• Instruction prefetching
• Load and store buffers
This chapter only address coherence in a uniprocessor environment. For more in-
formation about coherence in multi-processor environments, see Chapter 15,
“SPARC-V9 Memory Models.”
5.2 Cache Flushing
Data in the level-1 (read-only or write-through) caches can be flushed by invali-
dating the entry in the cache. Modified data in the level-2 (writeback) cache must
be written back to memory when flushed.
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