Sun Microsystems UltraSPARC-I - Debug and Diagnostics Support; Overview; Diagnostics Control and Accesses; Dispatch Control Register

Sun Microelectronics
303
Debug and Diagnostics Support A
A.1 Overview
All debug and diagnostics accesses are double-word aligned, 64-bit accesses.
Non-aligned accesses cause a mem_address_not_aligned trap. Accesses must use
LDXA/STXA/LDFA/STDFA instructions, except for the instruction cache ASIs
which must use LDDA/STDA/STDFA instructions. Using another type of load
or store will cause a
data_access_exception trap (with SFSR.FT=8, Illegal ASI size).
Attempts to accesses these registers while in non-privileged mode cause a
data_access_exception trap (with SFSR.FT=1, privilege violation). User accesses can
be done through system calls to these facilities. See Section 6.9.4, “I-/D-MMU
Synchronous Fault Status Registers (SFSR),” on page 58 for SFSR details.
Caution: A STXA to any internal debug or diagnostic register requires a
MEMBAR #Sync before another load instruction is executed and on or before the
delay slot of a delayed control transfer instruction of any type. This is not just to
guarantee that the result of the STXA is seen; the STXA may corrupt the load data
if there is not an intervening MEMBAR #Sync.
A.2 Diagnostics Control and Accesses
The UltraSPARC diagnostics control and data registers are accessed through
RDASR/WRASR or load/store alternate instructions.
A.3 Dispatch Control Register
ASR 18
16
Name: DISPATCH_CONTROL_REG
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