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9. Interrupt Handling
dler. All of the external interrupt packets are processed at the highest interrupt
priority level; they are then re-prioritized as lower priority interrupts in the soft-
ware handler. The following pseudo-code sequence illustrates interrupt receive
handling.
Code Example 9-2 Code Sequence for an Interrupt Receive
Read state of ASI_INTR_RECEIVE; Error if !BUSY
Read from IV data reg 0 at ASI_UDB_INTR_R, VA=0x40 (optional)
Read from IV data reg 1 at ASI_UDB_INTR_R, VA=0x50 (optional)
Read from IV data reg 2 at ASI_UDB_INTR_R, VA=0x60 (optional)
Determine the appropriate handler
Handle interrupt or Re-prioritize this trap and
set the SoftInt register
Store zero to ASI_INTR_RECEIVE to clear the BUSY bit
9.2 Interrupt Global Registers
In order to expedite interrupt processing, a separate set of global registers is im-
plemented in UltraSPARC. As described in Section 9.1.2, “Interrupt Vector Re-
ceive,” on page 162, the processor takes an implementation-dependent
interrupt_vector
trap after receiving an interrupt packet. Software uses a number of
scratch registers while determining the appropriate handler and constructing the
interrupt state.
UltraSPARC provides a separate set of eight Interrupt Global Registers (IG) that
replace the eight programmer-visible global registers during interrupt processing.
When an
interrupt_vector
trap is taken, the hardware selects the interrupt global
registers by setting the PSTATE.IG field. The PSTATE extension is described in
Section 14.5.9, “PSTATE Extensions: Trap Globals,” on page 251. The previous
value of PSTATE is restored from the trap stack by a DONE or RETRY instruction
on exit from the interrupt handler.
9.3 Interrupt ASI Registers
Note: Generally, a MEMBAR #Sync is needed after a store to an interrupt ASI
registers. See Section 5.3.8, “Instruction Prefetch to Side-Effect Locations,” on
page 38.
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