Sun Microelectronics
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Error Handling 11
11.1 Overview
UltraSPARC provides error checking for all memory access paths between the
CPU, E-Cache, UltraSPARC Data Buffer (UDB), and system bus. Errors are re-
ported as system fatal errors, deferred traps, or disrupting traps. System fatal er-
rors are reported when the system must be reset before continuing. Deferred
traps are reported for non-recoverable failures requiring immediate attention, but
not system reset. Disrupting traps are reported for errors that may need logging,
but do not otherwise affect processor execution.
Error information is logged in the Asynchronous Fault Address Register, Asyn-
chronous Fault Status Register and the UDB Error Register (see Section 11.3.3,
“Asynchronous Fault Address Register,” on page 182, Section 11.3.2, “Asynchro-
nous Fault Status Register,” on page 180, and Section 11.3.4, “UltraSPARC Data
Buffer (UDB) Error Register,” on page 184). Errors are logged even if their corre-
sponding traps are disabled.
11.1.1 System Fatal Errors
When an E-Cache tag parity or system address parity error occurs, system coher-
ency has been lost and the system should be reset. When these errors occur and
the corresponding error trap is enabled in the E-Cache Error Enable Register (see
Section 11.3.1, “E-Cache Error Enable Register,” on page 179), a P_REPLY of type
P_FERR is generated to the UPA. The system should generate a Power-on Reset
to all processors.
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