Sun Microelectronics
174
UltraSPARC User’s Manual
* This register is read-only from the system.
‡
Processor states are updated according to this table only when RED_state is entered on a reset or trap. If software
explicitly sets PSTATE.RED to 1, it must create the appropriate states itself.
†
If power has been cycled, the state of AFSR is unknown; otherwise, it is unchanged.
❶
This field or register is not present in UltraSPARC-I.
INTR_DISPATCH NACK
BUSY
Unknown
0
Unchanged
Unchanged
INTR_RECEIVE BUSY 0 Unchanged
MID Unknown Unchanged
ESTATE_ERR_EN ISAPEN
(sys addr err)
NCEEN (non CE)
CEEN (CE)
0 (off)
0 (off)
0 (off)
Unchanged
Unchanged
Unchanged
AFAR PA Unknown Unchanged
AFSR all Unchanged† Unchanged
Other UltraSPARC Specific States
Processor and E-Cache tags and data Unknown Unchanged
Cache snooping Enabled
Instruction Buffers Empty
Load/Store Buffers, all outstanding
accesses
Empty Unchanged Empty
iTLB, dTLB Mappings
E-bit (side-effect)
NC-bit (noncache-
able)
Unknown
1
1
Unchanged
1
1
RAS all RSTV | 20
16
Unchanged
Table 10-1 Machine State After Reset and in RED_state (Continued)
Name Fields POR WDR XIR SIR RED_state
‡
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