Sun Microelectronics
47
6. MMU Internal Architecture
The TSB Tag Target (described in Section 6.9, “MMU Internal Registers and ASI
Operations,” on page 55) is formed by aligning the missing access VA (from the
Tag Access register) and the current context to positions found in the description
of the TTE tag. This allows an XOR instruction for TSB hit detection.
These items must be locked in the TLB to avoid an error condition: TLB-miss han-
dler, TSB and linked data, asynchronous trap handlers and data.
These items must be locked in the TSB (not necessarily the TLB) to avoid an error
condition: TSB-miss handler and data, interrupt-vector handler and data.
6.3.2 Alternate Global Selection During TLB Misses
In the SPARC-V9 normal trap mode, the software is presented with an alternate
set of global registers in the integer register file. UltraSPARC provides an addi-
tional feature to facilitate fast handling of TLB misses. For the following traps, the
trap handler is presented with a special set of MMU globals:
fast_{instruction,da-
ta}_access_MMU_miss
,
{instruction,data}_access_exception
, and
fast_data_access_protection
. The
privileged_action
and *
mem_address_not_aligned
traps
use the normal alternate global registers.
Compatibility Note:
The
UltraSPARC MMU performs no hardware table walking. The MMU hard-
ware never directly reads or writes the TSB.
6.4 MMU-Related Faults and Traps
Table 6-3 lists the traps recorded by the MMU.
1
Contents undefined if
instruction_access_exception
is due to virtual address out of range.
Table 6-3 MMU Traps
Trap Name Trap Cause
Registers Updated
(Stored State in MMU)
I-SFSR
I-Tag
Access
D-SFSR,
SFAR
D-Tag
Access
fast_instruction_access_MMU_miss
iTLB miss ✓
instruction_access_exception
Several (see below) ✓✓
1
fast_data_access_MMU_miss
dTLB miss ✓
data_access_exception
Several (see below) ✓✓
fast_data_access_protection
Protection violation ✓✓
privileged_action
Use of privileged ASI ✓
*
_watchpoint
Watchpoint hit ✓
*
_mem_address_not_aligned
Misaligned mem op ✓
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