Sun Microelectronics
304
UltraSPARC User’s Manual
This control register is accessed through ASR 18
16
. Nonprivileged accesses to this
register cause a
privileged_opcode
trap. See also Table 10-1, “Machine State After Reset
and in RED_state,” on page 172 for the state of this register after reset.
Figure A-1 Dispatch Control Register (ASR 18
16
)
MS IEU.multi_scalar—Multi-Scalar Dispatch Control. If cleared, instruction
dispatch is forced to a single instruction per group.
A.4 Floating-Point Control
Two state bits (PSTATE.PEF and FPRS.FEF) in the SPARC-V9 architecture provide
the means to disable direct floating-point execution. If either field is cleared, an
fp_disabled
trap is taken when a floating-point instruction is encountered.
Note: Graphics instructions that use the floating-point register file and
instructions that read or update the Graphic Status Register (GSR) are treated as
floating-point instructions. They cause an
fp_disabled
trap if either PSTATE.PEF or
FPRS.FEF is cleared. See Section 13.5, “Graphics Instructions,” on page 198 for
more information.
A.5 Watchpoint Support
UltraSPARC implements “break before”
watchpoint
traps; instruction execution is
stopped immediately before the watchpoint memory location is accessed. Table
A-1 on page 305 lists ASIs that are affected by the two watchpoint traps. For
128-bit atomic load and 64-byte block load and store, a
watchpoint
trap is generat-
ed only if the watchpoint overlaps the lowest addressed 8 bytes of the access.
Note: In order to avoid trapping infinitely, software should emulate the
instruction at the watched address and execute a DONE instruction or turn off
the watchpoint before exiting a
watchpoint
trap handler.
63 0
MS
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