Sun Microelectronics
25
Section II — Going Deeper
5. Cache and Memory Interactions ...................................................... 27
6. MMU Internal Architecture ............................................................... 41
7. UltraSPARC External Interfaces ....................................................... 73
8. Address Spaces, ASIs, ASRs, and Traps .......................................... 145
9. Interrupt Handling ............................................................................. 161
10. Reset and RED_state .......................................................................... 169
11. Error Handling .................................................................................... 175
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