Sun Microsystems UltraSPARC-I - Power-Up; C.3 Power-Up

Sun Microelectronics
328
UltraSPARC User’s Manual
C.3 Power-Up
Restart from power-down mode uses the power-on reset (POR) pin. The system
must activate the reset pin with a stable external clock for the same time as a nor-
mal power-on reset. This reset will shut off the external power-down (EPD) sig-
nal (asynchronously if the module clock generator has been disabled), and enable
the clock generator and PLL, like a normal power-up sequence. Using the reset
pin instead of a synchronous wake-up signal eliminates the problems of warm
switching the PLL loops and sampling the wake-up signal without a clock.
When the reset pin is deasserted, UltraSPARC begins RED_state reset processing
just as in a normal power-on reset. The system must provide state information
that indicates to software whether this is a warm start from power-down mode,
or a cold start from a power-on reset.
After reset, software should re-enable transmission of interrupt vectors, and reset
the caches (I-Cache, D-Cache, E-Cache, I-MMU, and D-MMU) as in a normal
Power-on Reset (POR).
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