Sun Microelectronics
161
Interrupt Handling 9
9.1 Interrupt Vectors
Processors and I/O devices can interrupt a selected processor by assembling and
sending an interrupt packet consisting of three 64-bit words of interrupt data.
The contents of this data are defined by software convention. This allows hard-
ware interrupts and cross calls to have the same hardware mechanism for inter-
rupt delivery and to share a common software interface for processing. The
processor can post interrupts to itself at any level by writing to the SOFTINT
Register.
Note: Separate sets of dispatch (outgoing) and receive (incoming) interrupt data
registers allow simultaneous interrupt dispatching and receiving.
9.1.1 Interrupt Vector Dispatch
To dispatch an interrupt or cross call, a processor or I/O device first writes to the
Outgoing Interrupt Vector Data Registers according to an established software
convention described below. A subsequent write to the Interrupt Vector Dispatch
Register (described in Section 9.3.2, “Interrupt Vector Dispatch”) triggers the in-
terrupt delivery. The status of the interrupt dispatch can be read by polling the
ASI_INTR_DISPATCH_STATUS’s BUSY and NACK bits. A MEMBAR #Sync
should be used before polling begins to ensure that earlier stores are completed.
If both NACK and BUSY are cleared, the interrupt has been successfully deliv-
ered to the target processor. With the NACK bit cleared and BUSY bit set, the in-
terrupt delivery is pending. Finally, if the delivery cannot be completed (if it is
rejected by the target processor), the NACK bit is set. The pseudo-code sequence
in Code Example 9-1 on page 162 sends an interrupt.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...