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D. IEEE 1149.1 Scan Interface
D.4 Instruction Register
The instruction register is used to select the test to be performed and/or the test
data register to be accessed.
The instruction register is 8 bits wide and consists of a shift-register (with parallel
inputs) and a parallel output stage. The parallel outputs are loaded during the
UPDATE-IR state with the instruction shifted into the shift register stage. This en-
sures that the instruction only changes synchronously at the end of an instruction
register shift or on entry to the TEST-LOGIC-RESET state. The behavior of the in-
struction register in each controller state is shown in Table D-2.
At the start of an instruction register shift (that is, during the CAPTURE-IR state),
the least 2 significant bits load a constant ‘01’ pattern. This aids in fault isolation
of the board-level serial test data path.
D.5 Instructions
The UltraSPARC 8 bit instruction register (IR) implements numerous public and
private instructions. There are 75 valid instructions out of the 256 possible encod-
ings; all invalid encodings default to the BYPASS instruction as defined in IEEE
Std 1149.1-1990. The public instructions implemented are: BYPASS, IDCODE, EX-
TEST, SAMPLE and INTEST. Private instructions are used for manufacturing pur-
poses and should not be used without first consulting with your SPARC sales
representative. The instruction encodings and the test data register selected is
presented in Table D-3.
Table D-2 Instruction register behavior
Controller State Shift Register Parallel Output
TEST-LOGIC-RESET Undefined Set to 00
16
(select Device ID
register for shift)
CAPTURE IR Load 01 into IR <1:0> Retain last state
SHIFT IR Shift towards serial output Retain last state
UPDATE IR Retain last state Load from shift-register stage
All other states Retain last state Retain last state
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