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D. IEEE 1149.1 Scan Interface
D.5.1.4 INTEST
Selects the boundary scan register as the active test data register. This instruction
allows the boundary scan register to be used sa virtual low speed functional
tester. The on-chip clock is derived from TCK and is issued in the Run-Test/Idle
state of the TAP controller.
D.5.1.5 IDCODE
Select the ID register for shifting.
D.5.2 Private Instructions
All private instructions: PLLMODE, CLKCTRL, RAMWCP, POWERCUT, HIGHZ,
INTEST2, and all versions FULLSCAN should not be used without first consult-
ing your SPARC sales representative. Improper use of any of the private instruc-
tions could permanently damage UltraSPARC and render the device inoperative.
D.6 Public Test Data Registers
D.6.1 Device ID Register
A 32-bit register that is loaded with the UltraSPARC ID upon entering the CAP-
TURE-DR TAP state when the ID instruction is active or during the TEST-LOGIC-
RESET state. Figure D-2 shows the structure of the Device ID Register.
Figure D-2 Device ID Register
The device ID is loaded into the register on the rising edge of TCK in the Cap-
ture-DR state. The value of ID<27:0> is fixed at 002502F
16
and the version num-
ber, ID<31:28>, changes as specified in IEEE Std 1149.1-1990.
D.6.2 Bypass Register
Provides a single bit delay between TDI and TDO. During the CAPTURE-DR
controller state, the bypass register (if selected by the current instruction) will
load a logic zero.
011112272831
1000 0001 01110000 0000 0010 0101Version
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