Sun Microelectronics
282
UltraSPARC User’s Manual
• FMOVcc (Move Floating-Point Register on Condition)
— Consists of the following instructions: FMOV{s,d,q}A, FMOV{s,d,q}CC,
FMOV{s,d,q}CS, FMOV{s,d,q}E, FMOV{s,d,q}G, FMOV{s,d,q}GE,
FMOV{s,d,q}GU, FMOV{s,d,q}L, FMOV{s,d,q}LE, FMOV{s,d,q}LEU,
FMOV{s,d,q}N, FMOV{s,d,q}NE, FMOV{s,d,q}NEG, FMOV{s,d,q}POS,
FMOV{s,d,q}VC, and FMOV{s,d,q}VS.
Instruction Classes:
Groups of SPARC-V9 and UltraSPARC instructions that have similar effects.
Instruction classes are always written in lower case italic body font. Examples are:
• setcc (any instruction that sets the condition codes)
• alu (any instruction processed in the Arithmetic and Logic Unit)
17.1.2 Example Conventions
Instructions are shown with offsets between their stages, to indicate the amount
of latency that (normally) occurs between the instructions. The following instruc-
tion pair has one cycle of latency:
This instruction pair has no latency:
17.2 General Grouping Rules
Up to four instructions can be dispatched in one cycle, subject to availability from
the instruction buffer, execution resources, and instruction dependencies.
UltraSPARC has input (read-after-write) and output (write- after-write) depen-
dency constraints, but no anti-dependency (write-after-read) constraints on in-
struction grouping.
Instructions belong to one or more of the following categories:
• Single group
• IEU
• Control transfer
• Load/store
ADD i1, i2, i6 GECN
1
N
2
N
3
W
SLL i6, 2, i8 GECN
1
N
2
N
3
W
alu → r6 GECN
1
N
2
N
3
W
store → r6 GECN
1
N
2
N
3
W
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