Sun Microelectronics
250
UltraSPARC User’s Manual
INT_DIS: If set, TICK_INT interrupt generation is disabled.
TICK_CMPR: Writes to the TICK_Compare Register load a value for comparison
to the TICK register bits <62:0>. When these values match and
(INT_DIS=0) a TICK_INT is posted in the SOFTINT register. This has the
effect of posting a level-14 interrupt to the processor when the processor
has (PSTATE.PIL < D
16
) and (PSTATE.IE=1). The level-14 interrupt
handler must check both SOFTINT<14> and TICK_INT. This function is
independent on each processor.
14.5.2 Cache Sub-system
UltraSPARC contains one or more levels of caches. The cache sub-system archi-
tecture is described in Chapter 3, “Cache Organization.”
14.5.3 Memory Management Unit
UltraSPARC implements a multi-level memory management scheme. The MMU
architecture is described in Chapter 4, “Overview of the MMU.”
14.5.4 Error Handling
UltraSPARC implements a set of programmer-visible error and exception regis-
ters. These registers and their usage are described in Chapter 11, “Error Han-
dling.”
14.5.5 Block Memory Operations
UltraSPARC supports 64-byte block memory operations utilizing a block of eight
double-precision floating point registers as a temporary buffer. See Section 13.6.4,
“Block Load and Store Instructions,” on page 230.
Table 14-11 TICK_compare Register Format
Bits Field Use RW
<63> INT_DIS TICK_INT interrupt enable RW
<62:0> TICK_CMPR Compare value for TICK interrupts RW
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