Sun Microelectronics
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7. UltraSPARC External Interfaces
Table 7-16 shows the number of outstanding Writeback transactions that each
UltraSPARC model supports.
UltraSPARC-I issues only one Writeback transaction at a time. The Writeback and
its associated read transaction (with DVP=1) both must complete (receive their
respective S_REPLYs) before UltraSPARC-I issues a second read with DVP=1.
UltraSPARC-I can issue a subsequent read transaction with DVP=0 while there is
a previous Writeback pending.
UltraSPARC-I waits until it receives the acknowledgment (S_WAB or S_WBCAN)
for a Writeback transaction before it issues a coherent request for the previously
victimized block.
UltraSPARC-II can issue up to two Writeback transactions at a time; each of these
Writebacks can have an associated read with DVP=1. When two Writebacks are
outstanding, one must receive its S_REPLY before UltraSPARC-II issues a third
read with DVP=1.
UltraSPARC delays issue of a coherent read to any address that has an outstand-
ing Writeback.
UltraSPARC inhibits its own (internal) access to a victimized line (clean or dirty).
UltraSPARC keeps the victimized line in the coherence domain (and responds to
S_REQs for the line) until it receives the S_REPLY for either:
• The cache fill if the line was clean, or
• The Writeback if the line was dirty.
If UltraSPARC receives an invalidate request (S_INV_REQ or S_CPI_REQ) for a
dirty victim block with a pending Writeback, it does not cancel its Writeback.
When UltraSPARC issues the P_WRB_REQ, SC uses either S_WBCAN or S_WAB
to complete the Writeback, but it does not update memory.
SC can maintain the pending Writeback cancellation state in the Dtags; in systems
without Dtags, SC can use some other implementation-specific means.
Table 7-16 Supported Number of Outstanding Writeback Transactions
UltraSPARC-I UltraSPARC-II
Number 12
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