Sun Microelectronics
iv
UltraSPARC User’s Manual
5.2 Cache Flushing............................................................................................................. 27
5.3 Memory Accesses and Cacheability ......................................................................... 29
5.4 Load Buffer................................................................................................................... 39
5.5 Store Buffer................................................................................................................... 40
6. MMU Internal Architecture ................................................................................................ 41
6.1 Introduction.................................................................................................................. 41
6.2 Translation Table Entry (TTE) ................................................................................... 41
6.3 Translation Storage Buffer (TSB)............................................................................... 44
6.4 MMU-Related Faults and Traps................................................................................ 47
6.5 MMU Operation Summary........................................................................................ 50
6.6 ASI Value, Context, and Endianness Selection for Translation............................ 52
6.7 MMU Behavior During Reset, MMU Disable, and RED_state............................. 54
6.8 Compliance with the SPARC-V9 Annex F............................................................... 55
6.9 MMU Internal Registers and ASI Operations ......................................................... 55
6.10 MMU Bypass Mode..................................................................................................... 68
6.11 TLB Hardware.............................................................................................................. 69
7. UltraSPARC External Interfaces......................................................................................... 73
7.1 Introduction.................................................................................................................. 73
7.2 Overview of UltraSPARC External Interfaces......................................................... 73
7.3 Interaction Between E-Cache and UDB.................................................................... 76
7.4 SYSADDR Bus Arbitration Protocol......................................................................... 84
7.5 UltraSPARC Interconnect Transaction Overview .................................................. 92
7.6 Cache Coherence Protocol.......................................................................................... 94
7.7 Cache Coherent Transactions .................................................................................... 102
7.8 Non-Cached Data Transactions................................................................................. 109
7.9 S_RTO/S_ERR ............................................................................................................. 111
7.10 S_REQ............................................................................................................................ 111
7.11 Writeback Issues.......................................................................................................... 112
7.12 Interrupts (P_INT_REQ)............................................................................................. 116
7.13 P_REPLY and S_REPLY.............................................................................................. 117
7.14 Multiple Outstanding Transactions.......................................................................... 126
7.15 Transaction Set Summary........................................................................................... 129
7.16 Transaction Sequences................................................................................................ 131
7.17 Interconnect Packet Formats...................................................................................... 138
7.18 WriteInvalidate ............................................................................................................ 143
8. Address Spaces, ASIs, ASRs, and Traps ........................................................................... 145
8.1 Overview....................................................................................................................... 145
8.2 Physical Address Space .............................................................................................. 145
8.3 Alternate Address Spaces........................................................................................... 146
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