Sun Microelectronics
289
17. Grouping Rules and Stalls
the W
1
Stage
1
. If the branch in the previous example was predicted not taken but
actually was taken:
If an annulling branch is predicted not taken, the delay slot is still dispatched.
Multicycle instructions (except load instructions) run to completion, even if the
delay slot instruction is annulled. For example:
The imul unit is busy for the duration of the multiply.
An annulled delay slot other than a load affects subsequent dependency checking
until the delay slot reaches the W
1
Stage. For example:
In the example above, the FADD instruction is stalled in issue until the FDIV in-
struction completes.
A predicted annulled load does not affect dependency checking after it is dis-
patched. For example:
1. The W
1
Stage is a virtual stage that is normally not visible to the programmer.
setcc GECN
1
N
2
N
3
W
BPcc (mispredicted) GECN
1
N
2
N
3
W
FADD (delay slot) GECN
1
N
2
N
3
W
FMUL → f0 (sequential) GECN
1
N
2
N
3
WW
1
FMUL f0,f0,f0 (branch target) GE
BPcc, a (not taken) GECN
1
N
2
N
3
W
imul (delay slot) GEEEEEE...
BPcc, a (not taken) GECN
1
N
2
N
3
W
FDIV → f0 (delay slot) GECN
1
N
2
N
3
WW
1
FADD f0,f0,f1 (sequential) G
BPcc, a (predicted not taken) GECN
1
N
2
N
3
W
fld → f0 (delay slot) GECN
1
N
2
N
3
W
FADD f0,f0,f1 (sequential) GECN
1
N
2
N
3
W
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