Sun Microsystems UltraSPARC-I - Page 303

Sun Microelectronics
288
UltraSPARC User’s Manual
If the delay slot of a DCTI is aligned on a 32-byte address boundary (that is, the
DCTI is the last instruction in a cache line and the delay slot contains the first in-
struction in the next cache line), then the DCTI cannot be grouped with instruc-
tions from the predicted stream. For example:
If the second instruction of the predicted stream is aligned on a 32-byte address
boundary, then the DCTI cannot be grouped with that instruction. For example:
The delay slot of a DCTI cannot be grouped with instructions from the predicted
stream of another DCTI following the delay slot. For example:
When a control transfer is mispredicted, the instruction buffer and instructions
younger than the delay slot in the pipe are flushed, effectively inserting four bub-
bles in the pipe. An FDIV or FSQRT in the mispredicted stream cause dependent
instructions in the correct branch stream to stall until the FDIV or FSQRT reaches
setcc
GECN
1
N
2
N
3
W
BPcc GECN
1
N
2
N
3
W
FADD (32-byte aligned) GECN
1
N
2
N
3
W
FMUL (branch target) GECN
1
N
2
N
3
W
BPcc GECN
1
N
2
N
3
W
ADD (delay slot) GECN
1
N
2
N
3
W
FADD GECN
1
N
2
N
3
W
FMUL (32-byte aligned) GECN
1
N
2
N
3
W
FADD (delay slot 1) GECN
1
N
2
N
3
W
BPcc GECN
1
N
2
N
3
W
ADD (delay slot 2) GECN
1
N
2
N
3
W
FMUL (branch target) GECN
1
N
2
N
3
W
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com