Sun Microelectronics
118
UltraSPARC User’s Manual
Figure 7-22 P_REPLY Packet Format (Cycle 2 not present in all P_REPLYs)
P_REPLYs take either one or two interconnect clock cycles. The first cycle con-
tains the P_REPLY type, and the Class bit. The second cycle, if present, contains
the Master ID (MID) of the UltraSPARC that generated the original request.
Table 7-17 shows the P_REPLY encodings and the number of cycles in each pack-
et.
The Class values are indicated as follows:
• 0=hardwired to 0
• X=don't care
• C=Copied from the P_REQ packet
With the exception of P_FERR, UltraSPARC generates all P_REPLYs as an ac-
knowledgment to a previous SC request. UltraSPARC can assert P_FERR at any
time to indicate a fatal error requiring system reset. upon seeing P_FERR from
any UltraSPARC, SC should assert RESET_L to all interconnect ports.
Table 7-17 P_REPLY Encoding
Type Cycles Name Reply to Transaction Class Type
P_IDLE 1 Idle Default State 0 0000
P_FERR 1 Fatal Error All transactions, any time X 0100
P_RERR 2 Read Data Error P_NCBRD_REQ C 0101
P_SNACK 2 Coherent S_REQ Non Existent ACK S_REQ C 0111
P_RAS 2 Read ACK Single P_NCRD_REQ C 1000
P_SACK 2 Coherent S_REQ ACK S_REQ C 1010
P_IAK 2 Interrupt Acknowledge P_INT_REQ C 1100
P_SACKD 2 Coherent S_REQ Dirty Victim ACK S_REQ C 1101
Class
Type
Master ID (MID)
Cycle 2
Cycle 1
4
3
0
4
0
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...