Sun Microelectronics
13
Preface
• Chapter 15, “SPARC-V9 Memory Models,” describes the supported memory
models (which are documented fully in The SPARC Architecture Manual,
Version 9). Low-level programmers and operating system implementors
should study this chapter to understand how their code will interact with the
UltraSPARC cache and memory systems.
Section IV, “Producing Optimized Code,” contains detailed information for as-
sembly language programmers and compiler developers. Section IV contains the
following chapters:
• Chapter 16, “Code Generation Guidelines,” contains detailed information
about generating optimum UltraSPARC code.
• Chapter 17, “Grouping Rules and Stalls,”describes instruction
interdependencies and optimal instruction ordering.
Appendixes contain low-level technical material or information not needed for a
general understanding of the architecture. The manual contains the following ap-
pendixes:
• Appendix A, “Debug and Diagnostics Support,” describes diagnostics
registers and capabilities.
• Appendix B, “Performance Instrumentation,” describes built-in capabilities to
measure UltraSPARC performance.
• Appendix C, “Power Management,” describes UltraSPARC’s Energy Star
compliant power-down mode.
• Appendix D, “IEEE 1149.1 Scan Interface,” contains information about the
scan interface for UltraSPARC.
• Appendix E, “Pin and Signal Descriptions,” contains general information
about the pins and signals of the UltraSPARC and its components.
• Appendix F, “ASI Names,” contains an alphabetical listing of the names and
suggested macro syntax for all supported ASIs.
A Glossary, Bibliography, and Index complete the book.
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