Sun Microelectronics
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7. UltraSPARC External Interfaces
7.14.2 Minimal Ordering Requirements
An SC can be less strict about the ordering requirements for asserting S_REPLYs
in Class 0 and 1, with respect to the original address packet. This may allow sim-
pler SCs to be built. The details also may be useful for understanding how to gen-
erate useful test cases and which test cases are not possible.
Sun systems have a requirement to preserve the order of 16-byte noncacheable
loads and stores. (Both in Class 1.) This is documented in Solaris system require-
ments documents. Also, all 16-byte noncacheable stores must complete in the or-
der issued, because the data must come from a FIFO in the UDB in issue order.
Also, all 64-byte block stores (P_NCBWR_REQ and P_WRI_REQ) must complete
in the order issued, because the data must come from another FIFO in the UDB in
issue order. For instance, even if a Writeback is in Class 1 behind noncacheable
stores, it can be completed out of order. This may allow a simpler read with
Writeback solution in an SC.
UltraSPARC always issues a dirty victim read miss before its corresponding
Writeback. If the E-Cache data bus is busy or if the assertion of an external re-
quest takes away SYSADDR, the Writeback can be delayed.
A Writeback is not issued during outstanding block stores (P_NCBWR_REQ or
P_WRI_REQ) or interrupt sends (P_INT_REQ).
Block stores (P_NCBWR_REQ/P_WRI_REQ) are not issued during outstanding
Writebacks or interrupt sends. An interrupt send is not mixed with outstanding
block stores or Writebacks.
7.14.3 Class 1 Strong Ordering
SC must complete all prior 16-byte noncacheable stores (P_NCWR_REQ) before
completing a P_NCRD_REQ. This is necessary to meet a software requirement
that all noncacheable operations to I/O space be strongly ordered. The E-bit fea-
ture of UltraSPARC does not wait for prior noncacheable operations to complete
(as do MEMBARs); it relies on the system to enforce strong ordering (that is, to
ensure that completion order equals issue order). For a description of the E-bit
see Section 6.2, “Translation Table Entry (TTE),” on page 41.
While a 16-byte noncacheable load is outstanding (P_NCRD_REQ), UltraSPARC
will not issue any more transactions, so the reverse case—completing noncache-
able loads before noncacheable stores—does not occur.
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