Sun Microelectronics
144
UltraSPARC User’s Manual
• Requiring that software include MEMBARs around loads and stores that can
cause misses and block stores to the same line.
UltraSPARC blocks the issue of instruction fetch miss requests (P_RDSA_REQ)
while there are outstanding block stores; it also inhibits issuing block stores while
there are outstanding instruction fetch miss requests. Otherwise, the IVA bit sent
with a P_WRI_REQ might not be set when it should be, because a subsequent co-
herent miss to the same address might complete first.
Systems with Dtags ignore the IVA bit, so this is not an issue.
Note: This hazard occurs only in uniprocessor systems without Dtags. In
system with Dtags, the requirement for an S_INV_REQ is determined by Dtag
lookup. Since processors must work in both systems, however, they must not
issue P_WRI_REQ for the same block address as an already outstanding
P_RD*_REQ, and not issue any P_RD*_REQ for the same block address as an
already outstanding P_WRI_REQ, until the S_REPLY for the outstanding
transaction is received.
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