Sun Microelectronics
206
UltraSPARC User’s Manual
13.5.3.4 FEXPAND
FEXPAND takes four 8-bit unsigned integers in rs2, converts each integer to a 16-
bit fixed value, and stores the four 16-bit results in the rd register.
This operation, illustrated in Figure 13-6, is carried out as follows:
1. Left shift each 8-bit value by 4 and zero-extend the results to a 16-bit fixed
value.
2. Stores the results in the rd register.
Figure 13-6 FEXPAND Operation
13.5.3.5 FPMERGE
FPMERGE interleaves four corresponding 8-bit unsigned values in rs1 and rs2, to
produce a 64-bit value in the rd register. This instruction converts from packed to
planar representation when it is applied twice in succession; for example:
R1G1B1A1, R3G3B3A3 → R1R3G1G3B1B3 → R1R2R3R4B1B2B3B4
1
rs2
rd
0
3
5
1
1
63
rs2
rd
13
0000
1
5
07
4
7
0
1
7
5
2
3
3
1
0000
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