Sun Microelectronics
212
UltraSPARC User’s Manual
Figure 13-12 FMUL8ULx16 Operation
13.5.4.6 FMULD8SUx16
FMULD8SUx16 multiplies the upper 8 bits of each 16-bit signed value in rs1 by
the corresponding signed 16-bit fixed point signed integer in rs2. The 24-bit prod-
uct is shifted left by 8-bits to make up a 32-bit result. The result is stored in the
corresponding 32-bit of the destination rd register. The operation is illustrated in
Figure 13-13.
Figure 13-13 FMULD8SUx16 Operation
3
rd
rs1
1
1
5
2
30
7
rs2
***
*
5
5
3
9
4
7
6
3
sign-extended
8 msb
sign-extended
8 msb
sign-extended
8 msb
sign-extended
8 msb
3
rd
rs1
1
1
5
2
30
7
rs2
**
00000000
00000000
0
7
3
9
4
0
6
3
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