Sun Microelectronics
217
13. UltraSPARC Extended Instructions
Description:
The standard 64-bit version of these instructions perform one of sixteen 64-bit
logical operations between rs1 and rs2. The result is stored in rd. The 32-bit (sin-
gle-precision) version of these instructions performs 32-bit logical operations.
Note: For good performance, do not use the result of a single logical as part of
a 64-bit graphics instruction source operand in the next instruction group.
Similarly, do not use the result of a standard logical as a 32-bit graphics
instruction source operand in the next instruction group.
Traps
fp_disabled
13.5.7 Pixel Compare Instructions
Format (3):
opcode opf operation
FCMPGT16
0 0010 1000
Four 16-bit compare; set
rd
if
src1
>
src2
FCMPGT32
0 0010 1100
Two 32-bit compare; set
rd
if
src1
>
src2
FCMPLE16
0 0010 0000
Four 16-bit compare; set
rd
if
src1
≤
src2
FCMPLE32
0 0010 0100
Two 32-bit compare; set
rd
if
src1
≤
src2
FCMPNE16
0 0010 0010
Four 16-bit compare; set
rd
if
src1
≠
src2
FCMPNE32
0 0010 0110
Two 32-bit compare; set
rd
if
src1
≠
src2
FCMPEQ16
0 0010 1010
Four 16-bit compare; set
rd
if
src1
=
src2
FCMPEQ32
0 0010 1110
Two 32-bit compare; set
rd
if
src1
=
src2
Suggested Assembly Language Syntax
fcmpgt16
freg
rs1
,
freg
rs2
,
reg
r
d
fcmpgt32
freg
rs1
,
freg
rs2
,
reg
r
d
fcmple16
freg
rs1
,
freg
rs2
,
reg
r
d
10 11 0110 rs2rd rs1
31 141924 18 13 02530 29 4
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