Sun Microelectronics
229
13. UltraSPARC Extended Instructions
13.6.3 Atomic Quad Load
Format (3) LDDA:
Description:
These ASIs are used with the LDDA instruction to atomically read a 128-bit data
item. They are intended to be used by the TLB miss handler to access TSB entries
without requiring locks. The data is placed in an even/odd pair of 64-bit integer
registers. The lowest address 64-bits is placed in the even register; the highest ad-
dress 64-bits is placed in the odd register. The reference will be made from the
nucleus context. In addition to the usual traps for LDDA using a privileged ASI,
a
data_access_exception
trap will be taken for a noncacheable access, or use with
any instruction other than LDDA. A
mem_address_not_aligned
trap will be taken if
the access is not aligned on a 128-bit boundary.
Traps:
fp_disabled
PA_watchpoint
VA_watchpoint
mem_address_not_aligned
(Checked for opcode implied alignment if the
opcode is not LDFA or STDFA)
data_access_exception
Opcode imm_asi ASI Value Operation
LDDA
ASI_NUCLEUS_QUAD_LDD 24
16
128-bit atomic load
LDDA
ASI_NUCLEUS_QUAD_LDD_L 2C
16
128-bit atomic load, little
endian
Suggested Assembly Language Syntax
ldda [
reg_addr
]
imm_asi
,
reg
rd
ldda [
reg_plus_imm
] %asi,
reg
rd
11 01 0011 rs2rd rs1
4
imm_asi
5
i=0
11 01 0011rd rs1
31 141924 18 13 02530 29
simm_13
i=1
12
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