Sun Microelectronics
236
UltraSPARC User’s Manual
14.1.3 Trap Levels (Impdep #37, 38, 39, 40, 114, 115)
UltraSPARC supports five trap levels; that is, MAXTL=5. Normal execution is at
TL0. Traps at MAXTL–1 cause the CPU to enter RED_state. If a trap is generated
while the CPU is operating at TL = MAXTL, the CPU will enter error_state and
generate a Watchdog Reset (WDR). CWP updates for window traps that cause en-
ter error_state are the same as when error_state is not entered.
Note: The RED_state trap vector address (RSTVaddr) is 256MB below the top of
the virtual address space; this is, at virtual address FFFF FFFF F000 0000
16
, which
is passed through to physical address 1FF F000 0000
16
in RED_state.
A processor normally executes at trap level 0 (execute_state, TL0). The trap han-
dling mechanism in SPARC-V9 differs from SPARC-V8 when a trap or error con-
dition is encountered at TL0. In SPARC-V8, the CPU enters trap state and system
(privileged) software must save enough processor state to guarantee that any er-
ror condition detected while in the trap handler will not put the CPU into
error_state (i.e. cause a reset). Then the trap routine is entered to process the er-
roneous condition. Upon completion of trap processing, the state of the CPU is
restored before returning to the offending code or terminating the process. This
time-consuming operation is necessary because SPARC-V8 does not support
nested traps.
In SPARC-V9, a trap brings the CPU into the next higher trap level. The most im-
portant machine states (PC, next PC, PSTATE) are saved on the trap stack. There
is one set of trap state registers for each trap level, so that entering into a higher
trap level is a very fast and efficient process. Then the trap (or error) condition is
processed.
For a complete description of traps and RED_state handling, see Section 10.3,
“Machine State after Reset and in RED_state,” on page 171.
14.1.4 Trap Handling (Impdep #16, 32, 33, 35, 36, 44)
UltraSPARC supports precise trap handling for all operations except for deferred
or disrupting traps from hardware failures encountered during memory accesses.
These failures are discussed in Section 11.2, “Memory Errors,” on page 178.
UltraSPARC implements precise traps, interrupts, and exceptions for all instruc-
tions, including long latency floating-point operations. Five traps levels are sup-
ported, which allows graceful recovery from faults. The trap levels are shown in
Figure 14-1. UltraSPARC can efficiently execute kernel code even in the event of
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...
Need help?
General