Sun Microelectronics
239
14. Implementation Dependencies
ing address by XORing ones into the upper 20 bits. See also Section 6.9.4, “I-/D-
MMU Synchronous Fault Status Registers (SFSR),” on page 58 and Section 6.9.5,
“I-/D-MMU Synchronous Fault Address Registers (SFAR),” on page 60.
When a trap occurs on the delay slot of a taken branch or call whose target is out-
of-range, or the last instruction below the VA hole, UltraSPARC records the fact
that nPC points to an out of range instruction. If the trap handler executes a
DONE or RETRY without saving nPC, the
instruction_access_exception
trap will be
taken when the instruction at nPC is executed. If nPC is saved and subsequently
restored by the trap handler, the fact that nPC points to an out of range instruc-
tion is lost. To guarantee that all out of range instruction accesses will cause
traps, software should not map addresses within 2
31
bytes of either side of the VA
hole as executable.
An out of range address during a data access will result in a
data_access_exception
trap if PSTATE.AM is not set. Because the D-MMU SFAR contains only 44 bits,
the trap handler must decode the load or store instruction if the full 64-bit virtual
address is needed. See also Section 6.9.4, “I-/D-MMU Synchronous Fault Status
Registers (SFSR),” on page 58 and Section 6.9.5, “I-/D-MMU Synchronous Fault
Address Registers (SFAR),” on page 60.
14.1.7 TICK Register
UltraSPARC implements a 63-bit TICK counter. For the state of this register at re-
set, see Table 10-1, “Machine State After Reset and in RED_state,” on page 172.
NPT: Non-privileged Trap enable. If set, an attempt by non-privileged software
to read the TICK register causes a
privileged_action
trap. If clear,
nonprivileged software can read this register with the RDTICK
instruction. This register can only be written by privileged software. A
write attempt by nonprivileged software causes a
privileged_action
trap.
counter: 63-bit elapsed CPU clock cycle counter.
Note: TICK.NPT is set and TICK.counter is cleared after both a Power-On-Reset
(POR) and an Externally Initiated Reset (XIR).
Table 14-1 TICK Register Format
Bits Field Use RW
<63> NPT
Non-privileged Trap enable RW
<62:0> counter Elapsed CPU clock cycle counter
RW
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