Sun Microelectronics
252
UltraSPARC User’s Manual
Note: Exiting RED_state by writing 0 to PSTATE.RED in the delay slot of a
JMPL instruction is not recommended. A noncacheable instruction prefetch may
be made to the JMPL target, which may be in a cacheable memory area. This may
result in a bus error on some systems, which causes an
instruction_access_error
trap. The trap can be masked by setting the NCEEN bit in the ESTATE_ERR_EN
register to zero, but this will mask all non-correctable error checking. Exiting
RED_state with DONE or RETRY avoids this problem.
UltraSPARC provides Interrupt and MMU global register sets in addition to the
two global register sets specified by SPARC-V9. The currently active set of global
registers is specified by the AG, IG and MG bits according to Table 14-13,
“PSTATE Global Register Selection Encoding,” on page 252.
Note: The IG and MG fields are saved on the trap stack along with the rest of
the PSTATE register.
When an
interrupt_vector
trap (trap type=60
16
) is taken, UltraSPARC selects the In-
terrupt Global registers by setting IG and clearing AG and MG. When a
fast_instruction_access_MMU_miss
,
fast_data_access_MMU_miss
,
fast_data_access_protection
,
data_access_exception
, or
instruction_access_exception
trap
is taken, UltraSPARC selects the MMU Global Registers by setting MG and clear-
ing AG and IG. When any other type of trap occurs, UltraSPARC selects the Al-
ternate Global Registers by setting AG and clearing IG and MG. Note that global
register selection is the same for traps that enter RED_state.
Executing a DONE or RETRY instruction restores the previous {AG, IG, MG} state
before the trap is taken. These three bits can also be set or cleared by writing to
the PSTATE register with a WRPR instruction.
Table 14-13 PSTATE Global Register Selection Encoding
AG IG MG Globals in Use
0 0 0 Normal
001MMU
0 1 0 Interrupt
011Reserved
1 0 0 Alternate
101Reserved
110Reserved
111Reserved
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