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16. Code Generation Guidelines
3. Since there is one set of prediction bits for every two instructions, it is
possible to have two branches (a CTI couple) sharing prediction bits.
Under normal circumstances, the bits are maintained correctly; however,
the bits may be updated based on the wrong branch if the second branch in
the CTI couple is the target of another branch (Figure 16-4).
Figure 16-4 Aliasing of Prediction Bits in a Rare CTI Couple Case
As stated in Chapter 17, “Grouping Rules and Stalls,” if the address of the in-
structions in a group cross a 32-byte boundary, an implicit branch is “forced” be-
tween instructions at address 31 and 32 (low order bits). That rule has a
performance impact only if a branch is in that specific group. Care should be tak-
en not to place a branch in a group that crosses this boundary. Figure 16-5 shows
an example of this rule. A group containing instructions I0 (branch), I1, I2, and I3
will be broken, because an artificial branch is forced after address 31 and there is
already a branch in the group.
Figure 16-5 Artificial Branch Inserted after a 32-byte Boundary
16.2.3 I-Cache Timing
If accesses to the I-Cache hit, the pipeline will rarely starve for instructions. Only
in pathological cases will the PDU be unable to provide a sufficient number of in-
structions to keep the functional units busy. For example, a taken branch to a tak-
en branch sequence without any instructions between the branches (except for
the delay slot) could only be executed at a peak rate of two instructions per cycle.
Otherwise, up to 4 instructions are sent to the D Stage to be decoded and eventu-
ally dispatched in the G Stage and executed starting in the E Stage.
An I-Cache miss does not necessarily result in bubbles being inserted into the
pipeline. Part of the I-Cache miss processing, or even all of it, can be overlapped
with the execution of instructions that are already in the instruction buffer and
are waiting to be grouped and executed. Moreover, since the operation of the
Branch Branch
Prediction
Entry Point
I3
I1 I2 I3
..30 ..31 ..0 ..1 ..2
Group Break Forced
Branch
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