Sun Microelectronics
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16. Code Generation Guidelines
2. Avoid scheduling long latency instructions such as FDIV if the branch is
predicted to be not-taken a significant portion of the time (since they affect
the timing of the non-taken stream).
3. Avoid scheduling an instruction that would stall dispatching due to a load-
use dependency.
4. Avoid scheduling WR(PR, ASR), SAVE, SAVED, RESTORE, RESTORED,
RETURN, RETRY, and DONE in the delay slot and in the first three groups
following an annulling branch.
16.2.6.2 Conditional Moves vs. Conditional Branches
The MOVcc and MOVR instructions provide an alternative to conditional branch-
es for executing short code segments. UltraSPARC differentiates the two as fol-
lows:
• Conditional branches: the branches are always resolved in the C stage.
Distancing the SETcc from Bicc does not gain any performance. The penalty
for a mispredicted branch is always 4 cycles. SETcc, Bicc, and the delay slot
can be grouped together (Figure 16-7).
Figure 16-7 Handling of Conditional Branches
• Conditional moves: MOVcc and MOVR are dispatched as single instruction
groups. Consequently, SETcc and MOVcc (or MOVR) cannot be grouped
together (vs. SETcc and Bicc). Also, a use of the destination register for the
MOVcc follows the same rule as a load-use (breaks group plus a bubble).
Figure 16-8 shows a typical example.
Figure 16-8 Handling of MOVCC
The use of FMOVR is more constrained than MOVcc. Besides having to wait for
the load buffer to be empty, FMOVR and any younger IEU instructions must be
separated by one group, even if there is no dependency between the IEU instruc-
tion and FMOVR.
setcc GECN
1
N
2
N
3
W
bicc GECN
1
N
2
N
3
W
delay GECN
1
N
2
N
3
W
setcc GECN
1
N
2
N
3
W
movcc GECN
1
N
2
N
3
W
use GECN
1
N
2
N
3
W
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