Sun Microelectronics
280
UltraSPARC User’s Manual
Code Example 16-4 RAW Hazard Penalty
Under the Relaxed Memory Order (RMO) mode, stores can pass younger loads if
a MEMBAR instruction has not been issued to prevent it. UltraSPARC provides
hardware detection of Write-After-Read (WAR) hazards so that a store to the
same memory address as an older outstanding load does not pass that load. If a
WAR hazard is detected, the store waits in the store buffer until the older load
completes. The CPI penalties resulting from this only have a second-order effect
on performance. The store buffer may fill up (rare), or an extra RAW hazard
could be generated because stores stay in the store buffer longer.
16.3.9 Non-Faulting Loads
The ability to move instructions “up” in the instruction stream beyond condition-
al branches can effectively hide the latencies of long operations. This also increas-
es the number of candidate instructions that the compiler can schedule without
conflicts. SPARC-V9 provides non-faulting loads (equivalent to silent loads used for
Multiflow TRACE and Cydrome Cydra-5), so that loads can be moved ahead of
conditional control structures that guard their use. Non-faulting loads execute as
any other loads, except that catastrophic errors, such as segmentation fault condi-
tions, do not cause the program to terminate. The hardware and software (trap
handler) cooperate so that the load appears to complete normally with a zero re-
sult. In order to minimize page faults when a speculative load references a NULL
pointer (address zero), system software should map low addresses (especially ad-
dress zero) to a page of all zeros and use the Non-Faulting Only (NFO) page at-
tribute bit.
Simulations of general code percolation for UltraSPARC have shown that there is
much to be gained by using non-faulting loads. For integer programs the average
group size (AGS) sent down the pipeline is 33% larger when code motion is al-
lowed across one branch (using speculative loads) and 50% larger when instruc-
tions can be moved ahead of two branches.
st %l1,[addr1]
ld [addr1],%l2
add %l2,%l3,%l4
RAW Hazard
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